The growing market for high performance personal computers has created a demand for a new generation of dynamic random access memories (DRAMs) with wide bit organization. A wider I/O DRAM, greater than X16, is necessary to provide sufficiently small granularity for a memory system. Granularity is the minimum increment of memory that may be added to a system.
Hierarchical data-line architectures which transfer many bits over a memory array could potentially be used to provide a wide I/O. However, even using these schemes, chip size must be expanded to accommodate additional elements and wiring as I/O width increases.
The recent demand for higher density integration semiconductor memory devices has necessitated denser patterns of arrangement for bit lines, word lines, and sense amplifiers, etc. There are various known bit line layout configurations including open bit line structure shown in FIG. 1a and folded bit line structure shown in FIG. 1b. According to the open bit line structure as shown in FIG. 1a, the bit line pairs (B0, /B0), (B1, /B1), (B2, /B2), . . . extend from both sides of the sense amplifiers and the column switches 1. The column switches 1 select the bit line pairs and connect the selected bit line pair to data lines (not shown). W0, W1, W2, . . . are word lines. According to the folded bit line structure as shown in FIG. 1b, the bit line pairs (B0, /B0), (B1, /B1), (B2, /B2), . . . extend in one direction in parallel away from the sense amplifiers 3 toward the column switches 5. Word lines are shown by W0, W1, W2, etc. In each bit line layout scheme, the arrangement of sense amplifiers is restricted by the space between the bit lines, i.e., the memory cell pitch. If a folded bit line structure is employed, the space between adjacent sense amplifiers cannot be relaxed in excess of two memory cell pitches. Further, conventional sense amplifiers are arranged one by one in the longitudinal direction of the bit lines in the spaces between the bit lines forming the memory cell array. Hence, it has been difficult to reduce the plane area of the region provided with the sense amplifiers.
To realize fast access time and a wide I/O operation, it is necessary to enhance the layout efficiency of chip architecture. If a wide data path were formed in the chip periphery, it would occupy extra area and result in an increased wiring capacitance due to the detour. To address this problem, local data lines (LDQs) assigned to the various bit line pairs are now being supplemented by master data lines (MDQs).
An example of an architecture including LDQs (LDQ, /LDQ) and MDQs (MDQ, /MDQ) is depicted in FIG. 2. This architecture type enables the MDQs to pass through cell arrays (i.e., the intersection of bit lines and word lines) and/or sense amplifiers S/A saving chip area versus when the data lines are formed on the chip periphery. However, it is necessary to find space to implement the block select switch transistors MDQSWs which connect the LDQs and the MDQs. A specific example of a 64 Mb DRAM architecture employing a segment data bus (i.e., LDQ) and a global data bus (MDQ) is described in "A 40-ns 64-Mb DRAM with 64-b Parallel Data Bus Architecture" by M. Taguchi et al. in IEEE Journal of Solid State Circuits, Vol. 26, No. 11, Nov. 1991, pp. 1493-1497.
In an exemplary design for a 256 Mb DRAM, equalizers, isolators/multiplexers, sense amplifiers and a DQ gate (bit switch), etc. are required elements for each bit-line pair. A sense amplifier region of the 256 Mb DRAM including the required elements is shown in FIG. 3 and more particularly described below. Each set of required elements must be laid out within a certain pitch that is determined by the pitch x of each bit line pair BL, /BL where the pitch x is measured in micrometers (.mu.m). In other words, n sets of these elements are laid out within the width of (n*x) .mu.m and form a single unit. Thereafter, a series of units are positioned repeatedly next to each other as shown in FIG. 4.
Only one master data line (MDQ) switch is necessary for a group of bit line pairs. Assuming that one MDQ switch is necessary for m pairs of bit lines, the MDQ switch is laid out within the width of (m*x) .mu.m in a break area BA shown in FIG. 5a, or a word line stitch region SR in FIG. 5b.
According to the FIG. 5a arrangement, since only one MDQ switch is laid out in the break area, the area penalty is very large and the total length y of the unit block becomes larger.
In the FIG. 5b arrangement, the number and dimension of MDQ switches are determined by the number and area of the word line stitch regions SR, resulting in limited design. More specifically, the number of word line stitch regions is determined by considering the word line delay independent of the number of MDQ switches. Thus, if MDQ switches are laid out in word-line stitch regions, the total number of MDQ switches is limited since the word line stitch region is relatively narrow. The limited number of MDQ switches which can be implemented is not large enough to satisfy the needs for a wide I/O DRAM.